The conventional analog divider is constructed from MOSFETs and operates with the MOSFETs in their triode region, and thus only accepts the input signals limited within a certain range, making it only suitable for AC small signal applications. For DC large signal applications, the digital divider is usually used instead. However, the digital divider is disadvantageous because it requires greater space on a chip.
To improve the input range of the analog divider, as shown in FIG. 1, capacitors C1 and C2 are employed at the inputs of the analog divider, whose waveform diagram is shown in FIG. 2. In this analog divider, the input signals are currents id and in and are applied to the capacitors C1 and C2 to charge thereto to generate voltages Vc1 and Vc2, respectively, a signal Reset controls a switch M1 shunt to the capacitor C1, and a comparator 10 compares the voltage Vc1 with a threshold voltage Vth to generate a comparison signal VT to control a switch M2 shunt to the capacitor C2. With the signal Reset to switch the switch M1, the capacitor C1 is charged or reset to control the voltage Vc1. As shown in FIG. 2, at time t1, the voltage Vc1 increases to the threshold voltage Vth and thus turns on the comparison signal VT to turn on the switch M2 to reset the capacitor C2. At time t2, the signal Reset turns on the switch M1 to reset the capacitor C1 and thus turns off the comparison signal VT to turn off the switch M2, from which the voltage Vc2 increases until next time the voltage Vc1 becomes greater than the threshold voltage Vth. Assuming that the signal Reset has a pulse width TR, the comparison signal VT has an off time Td, and TR<<Td, referring to FIGS. 1 and 2, the capacitor C1 will be charged with a charging timeTcharge=Td−TR=C1×Vth/id,  [Eq-1]from which it is derived the off timeTd=(C1×Vth/id)+TR.  [Eq-2]
Therefore, the voltage Vc2 will have a peak valueVc2_peak=Td×in/C2.  [Eq-3]By applying the equation Eq-2 to the equation Eq-3, it is obtained the peak valueVc2_peak(C1×Vth/C2)×in/id,  [Eq-4]which shows that the peak value Vc2_peak of the voltage Vc2 is almost in direct proportion to the ratio in/id. In other words, the peak value Vc2_peak of the voltage Vc2 includes the information of the value produced by dividing the current in by the current id. Therefore, a peak detector is required to detect the peak value Vc2_peak of the voltage Vc2 for this divider. However, a general peak detector is constructed by a diode-capacitor network, and thus may fail to work if the input currents id and in are too small to produce a sufficient voltage Vc2. Alternatively, a peak detector may be implemented with sampling and holding circuit; however, it requires additional time for sampling and is thus unable to have instant response.
On the other hand, when the analog divider of FIG. 1 is just after startup or suffers any input transient, as shown in FIG. 2, it requires a delay time Tdelay for the capacitors C1 and C2 to be reset before they are recharged to produce the proper peak value Vc2_peak of the voltage Vc2, and the delay time Tdelay may be as long as the period of the signal Reset. Therefore, the analog divider of FIG. 1 is not suitable to applications where rapid response is needed.
Therefore, it is desired a wide range and fast response divider.